Application-specific integrated circuits

Results: 303



#Item
31IP library List of DELTA’s Intellectual Properties Overview •

IP library List of DELTA’s Intellectual Properties Overview •

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Source URL: assets.madebydelta.com

Language: English - Date: 2015-05-08 06:54:16
32Engineers’ Guide to FPGA & PLD Solutions Automotive Electronics Fuels Need for High-Reliability Devices  FPGAs: Good Company in

Engineers’ Guide to FPGA & PLD Solutions Automotive Electronics Fuels Need for High-Reliability Devices FPGAs: Good Company in

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Source URL: eproductalert.com

Language: English - Date: 2015-01-22 13:00:52
332011 NA62 Status Report to the CERN SPSC Abstract NA62 will study the rare decay K + → π + ν ν¯ at the CERN SPS. We report here progress on the construction and the preparations for the experiment since November 20

2011 NA62 Status Report to the CERN SPSC Abstract NA62 will study the rare decay K + → π + ν ν¯ at the CERN SPS. We report here progress on the construction and the preparations for the experiment since November 20

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Source URL: na62.web.cern.ch

Language: English - Date: 2011-03-28 09:08:57
34Design Flow for Modern Visual Displays Timothé Jahan ABSTRACT In the early days of simulators, there were no design tools fitting Visual Display Systems (VDS) design. This made it challenging to accurately predict syste

Design Flow for Modern Visual Displays Timothé Jahan ABSTRACT In the early days of simulators, there were no design tools fitting Visual Display Systems (VDS) design. This made it challenging to accurately predict syste

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Source URL: image-society.org

Language: English - Date: 2015-03-04 06:20:44
35Project result  CT302 I Towards one European test solution [TOETS] A testing dilemma As semiconductor chip

Project result CT302 I Towards one European test solution [TOETS] A testing dilemma As semiconductor chip

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Source URL: www.aeneas-office.eu

Language: English - Date: 2014-07-21 10:33:01
36Yosys - A Free Verilog Synthesis Suite Clifford Wolf, Johann Glaser† Johannes Kepler University, Austria Institute for Integrated Circuits ,  †

Yosys - A Free Verilog Synthesis Suite Clifford Wolf, Johann Glaser† Johannes Kepler University, Austria Institute for Integrated Circuits , †

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Source URL: www.clifford.at

Language: English - Date: 2013-10-11 16:34:33
37ALINT™ Design Rule Checking  Methodology Detects Design Flaws Early Aldec’s ALINT™ design analysis tool identifies critical design

ALINT™ Design Rule Checking Methodology Detects Design Flaws Early Aldec’s ALINT™ design analysis tool identifies critical design

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Source URL: www.aldec.com

Language: English - Date: 2014-09-11 15:01:15
38CapacityPrototyping FPGAs FPGA I/O Connectivity HES-7™ ASIC  DUAL FPGA

CapacityPrototyping FPGAs FPGA I/O Connectivity HES-7™ ASIC DUAL FPGA

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Source URL: www.aldec.com

Language: English - Date: 2015-05-04 18:05:31
39Chapter 1  Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures Johann Glaser, Clifford Wolf∗

Chapter 1 Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures Johann Glaser, Clifford Wolf∗

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Source URL: www.clifford.at

Language: English - Date: 2013-12-08 09:21:06
402013年2月xx日

2013年2月xx日

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Source URL: www.csis.tohoku.ac.jp

Language: English - Date: 2013-02-20 00:31:04